This invention relates to personal computers, and more particularly to personal computers in which improved capability is provided for local processor bus interfacing from alternate bus masters connected directly through planar and riser card connectors, thereby expanding utilization of components and software designed specifically for bus masters developed for a different bus architecture, whereby AT.TM. and compatible architectures, can benefit from programs generated for Micro Channel.TM. architecture.
Personal computer systems in general, and International Business Machines Corporation (IBM) personal computers in particular, have attained widespread use for providing computer power to many segments of today's society. Personal computer systems can usually be defined as desk tops, floor standing, or portable microcomputers that are generally comprised of a system unit having a single system processor and associated volatile and non-volatile memory, a display monitor, a keyboard, one or more diskette drives, a fixed disk storage, and an optional printer. One of the distinguishing characteristics of these systems is a motherboard or system planar to facilitate the connection of these components together. These systems are designed primarily to give independent computing power to a single user and are relatively inexpensively priced and adapted for use and purchase by individuals or small businesses. Examples of such personal computer systems are IBM's PERSONAL COMPUTER AT.TM. and IBM's PERSONAL SYSTEM/2.TM. Models 25, 30, L40SX, 50, 55, 65, 70, 80, 90 and 95. These before mentioned marks, and all those which are similarly marked by .TM. in this specification, are trademarks of IBM.
These computer systems can be classified into two general families. The first family, usually referred to as Family I Models, use a bus architecture exemplified by the IBM PERSONAL COMPUTER AT and other industry identified "IBM compatible" machines. The second family, referred to as Family II Models, use IBM's MICRO CHANNEL.TM. bus architecture exemplified by IBM'S PERSONAL SYSTEM/2 Models 50 through 95 computer systems and industry generated clones.
Early introductions of the Family I models typically used the popular INTEL 8088 or 8086 microprocessor as the system processor. These processors have the ability to address one megabyte of memory. Later Family I models and the Family II models typically use the higher speed INTEL 80286, 80386, and 80486 microprocessors which can operate in a real mode to emulate the slower speed INTEL microprocessors such as the 8086 or a protected mode which extends the addressing range from 1 megabyte to 4 gigabytes for some models. In essence, the real mode feature of Intel's 80286, 80386, and 80486 processors provide hardware compatibility with software written for the 8086 and 8088 microprocessors.
As personal computer technology has developed and moved from eight to sixteen and eventually thirty two bit wide bus interaction and to higher speed microprocessors capable of real and protected mode operation, performance capability has been sought by separating the architecture of the personal computer into varying bus areas. More specifically, in the early IBM PC computer system, what came to be known as the expansion bus was essentially a direct extension of the microprocessor 8086 or 8088 connections, buffered and demultiplexed as required. Later, as the AT bus specification was developed and came into wide use (also known as the Industry Standard Architecture or ISA), it became possible to sever the nearly direct connection between the microprocessor and the bus, giving rise to the presence of what became known as the local processor bus and the renaming of the expansion bus as the input/output bus.
Typically, in order to enhance performance, the local processor bus runs at a higher clock speed (typically expressed in Hertz) than does the input/output bus. The IBM AT architecture also opened the possibility of running more than one microprocessor on the input/output bus, through use of direct memory access (DMA) interrupts.
As enhanced performance capability continues to be a goal, and as faster clock speeds have become attainable for microprocessors, strategies have evolved in which it is desirable to accommodate Family II capabilities into Family I systems. In order to do this bus master control is necessary. To date this has been accomplished through planar redesign and usually unwieldy, awkward and expensive re-working of the circuitry. Channel attachment is not preferred, in particular in AT bus systems, since bus mastering on the AT bus is difficult to implement and multiple bus masters may be near to impossible to incorporate, while still maintaining compatibility. Connector re-work also can consume large areas of board space.
The texts The Micro Channel.TM. Architecture Handbook by C. Heath and W. L. Rosch and The Winn Rosch Hardware Bible by W. L. Rosch, both published by Brady, cover and explain bus architectures and other components and systems, e.g., alternate bus masters, as contemplated by this invention.